Mini Lab: Sequential Logic

Assigned:
Friday, Sep 15, 2017
Due:
You do not need to submit any work for this mini lab.
Summary:
For this mini lab you will implement a variety of memory circuits.
Collaboration:
You can work individually or in groups of your choice, with up to three students.
Submitting:
You do not need to turn in any work for this lab. If you are unable to finish all of the exercises during class time, I recommend that you complete this work on your own.

Preparation

Start Logisim with the following command:

$ java -jar /home/curtsinger/bin/logisim.jar

Background

For combinational logic, which is a simple mapping of logical inputs to outputs, we can talk about the truth table as the function specifying the input/output mapping. For sequential logic, the outputs become inputs. However, we can still talk about how the state maps to updated values in something we call the characteristic table, sequential logic’s analog to the truth table of combinational logic.

Other than listing the current value of an output on the left (with the inputs), and the updated/next value of the output on the right (as an output), there is no clearly identified standard for distinguishing these before/after values. We will use and to refer to the current and next states of an output for this lab.

Exercise 1: S-R Latch

a. Use Figure C.8.1 from your text to complete the characteristic table for an S-R latch:

$$S$$ $$R$$ $$Q$$ $$\bar{Q}$$ $$Q_{next}$$ $$\bar{Q}_{next}$$
0001
0010
1001
1010
0101
0110

Note that we don’t include any rows for because bad things can happen (see C.11).

b. Create a logisim project, then build an S-R latch in a subcircuit called s-r latch. For your latch to work, you will need to build your circuit in a specific order:

  • Gates
  • Input pins (labeled)
  • Output pins (labeled)
  • Connect input pins to gates
  • Connect output pins to gate outputs
  • Connect gate outputs to gate inputs

c. Test the various configurations of S and R to verify your characteristic table

d. Save your Logisim project (and save frequently!)

Exercise 2: D Latch

a. Complete the characteristic table for a D latch:

$$C$$ $$D$$ $$Q$$ $$Q_{next}$$
000
001
010
011
100
101
110
111

b. In the same Logisim project, create a subcircuit called d latch. Drop your s-r latch subcircuit into this circuit and add the additional inputs, outputs, and wires to implement a D latch.

c. Test the various settings of and to verify your characteristic table.

d. Save!

Exercise 3: D Flip Flop

a. In the main subcircuit, build a D flip flop with two D latches (see figure C.8.4).

  • Be sure to label your input and output pins
  • Be Careful! The book flips their and inputs in the diagram.

b. Test the various configurations of and to verify your flip flop is behaving correctly.

c. Without using your Logisim circuit, predict what will happen if you raise , then raise , but then lower before lowering ? Verify your prediction with Logisim.