HW 11 - Caches and Virtual Memory
Due at 10:30pm on Monday, December 7, 2015

For this assignment, you will submit your cache implementation from lab along with a description of your improvement to the cache and step-by-step instructions for testing your cache.

Collaboration

You should work with your partner(s) from lab to complete this assignment.

Grading

You will be evaluated on the correctness of your Logisim implementation, your description of the improvement you make to your cache, and the quality of your testing procedure.

Submitting your work

Email your work to me with the subject [CSC 211.01] Assignment 11. Include every group member in the email. Attach your logisim file, but include the rest of your work in the body of the email, not as an attachment.

Part A: Cache Implementation

Submit your cache implementation from lab, including at least one improvement to the cache. Other cache improvements are acceptable if I approve them before you submit your assignment.

Part B: Discussion of Cache Improvement

Briefly describe the purpose and implementation of the improvement you made to your cache. This text should help me understand your Logisim file, and make it clear why this would be a useful feature to have in your cache. Make sure you use labels in your Logisim file so you can refer to components of your circuit in the text.

Part C: Test Your Cache

For this part of the assignment, you will identify all of the different circumstances that you need to test to validate your cache, then write concrete testing procedures to verify that your cache is working.

1. Testing Circumstances

Your cache will behave differently depending on the inputs and its internal state. For example, a cache entry with a valid bit that is not set should return a miss, update the cached data and tag, then set the valid bit. Enumerate all of the different circumstances and explain how your cache shoud behave in each situation.

2. Test Procedure

For each circumstance you identified in part C.1, write a set of steps to run your cache through this circumstance, along with the expected cache behavior. Each test procedure should start from an empty cache, which will have all registers (valid, tag, and data registers in each entry) set to zero. You should pre-load your RAM element with the data required for your tests.

You may find it useful to view the internal state of a specific subcircuit element, both for your own evaluation and in your testing procedures. If you right click on a cache entry subcircuit, you can select View cache-entry, which will show the current state of this specific cache entry instead of the default starting state. You may need to manually clear the valid register in your cache entries if you change the contents of RAM after caching the old data from RAM.

Acknowledgements

This assignment was developed in collaboration with Jerod Weinman, and is licensed under the Creative Commons Attribution-Noncommercial-Share Alike 4.0 International License.