| Day | Date | Topic | Reading | Reading Journal | Homework | Significant Bits |
|---|---|---|---|---|---|---|
| Week 0 | ||||||
| F | 8/28 | Introduction (slides) | Electricity Voltage, Current, and Resistance |
Charlie | ||
| Week 1 | ||||||
| M | 8/31 | Circuits & Transistors (slides) | Transistors | Journal: Transistors | HW 0 | |
| W | 9/2 | Truth Tables & Boolean Algebra (slides) | C.1–C.2 | |||
| F | 9/4 | Reducing Boolean Expressions | Null & Lobur, “Focus on Karnaugh Maps” | Journal: Karnaugh Maps | ||
| Week 2 | ||||||
| M | 9/7 | Combinational Logic | C.3 | HW 1 | ||
| W | 9/9 | Combinational Logic (in-class lab) | 2.4, 3.2 (both optional) | Khoa | ||
| F | 9/11 | Instructions & the ALU | 1.2, C.5 (C-26 to C-29) | Journal: Instructions and the ALU | ||
| Week 3 | ||||||
| M | 9/14 | Designing a 32-bit ALU | C.5 (C-29 to C-35) | Journal: 32-bit ALU | HW 2 | Marcel |
| W | 9/16 | Sequential Logic (in-class lab) | C.7–C.8 | |||
| F | 9/18 | Class Canceled | C.9 | Journal: SRAM and DRAM | ||
| Week 4 | ||||||
| M | 9/21 | SRAM & DRAM (slides) | 1.4 | HW 3 | Tiffany, Anita | |
| W | 9/23 | Power, Performance, and Multicore (slides) | 1.5–1.9 | Alex | ||
| F | 9/25 | Exam 1 | ||||
| Week 5 | ||||||
| M | 9/28 | Assembly Language (slides) | 2.1–2.3 | Journal: Assembly Language | ||
| W | 9/30 | Machine Language (slides) | 2.5–2.6 | HW 4 | Ying | |
| F | 10/2 | Making Decisions (slides) | 2.7 | Journal: Making Decisions | Chris | |
| Week 6 | ||||||
| M | 10/5 | Implementing Procedures (slides) | 2.8 | |||
| W | 10/7 | Addressing (slides) | 2.10 | HW 5 | ||
| F | 10/9 | Program Translation (slides) | 2.12–2.13 | |||
| Week 7 | ||||||
| M | 10/12 | Exam 2 | ||||
| W | 10/14 | Arrays vs. Pointers (slides) | 2.14 | Uzo | ||
| F | 10/16 | Multiplication & Division (slides) | 3.3–3.4 | HW 6 | Samee | |
| Fall Break | ||||||
| Week 8 | ||||||
| M | 10/26 | Instruction Set Architectures (slides) | 2.16–2.19 | Renn | ||
| W | 10/28 | Processor & Logic Design (in-class lab) | 4.1–4.2 | Mark | ||
| F | 10/30 | The Datapath (slides) | 4.3 | |||
| Week 9 | ||||||
| M | 11/2 | Control (slides) | 4.4 | HW 7 | ||
| W | 11/4 | Exam 3 | ||||
| F | 11/6 | Pipelining (slides) | 4.5 | Fin | ||
| Week 10 | ||||||
| M | 11/9 | Pipelined Datapath & Control (slides) | 4.6 | No HW 8 | ||
| W | 11/11 | Data Hazards (slides) | 4.7 | Victoria | ||
| F | 11/13 | Control Hazards & Exceptions (slides) | 4.8–4.9 | |||
| Week 11 | ||||||
| M | 11/16 | Advanced Pipelining & ILP (slides) | 4.10–4.14 (4.12 is optional) | HW 9 | David | |
| W | 11/18 | Caches (slides) | 5.1–5.2 | |||
| F | 11/20 | Cache Performance (slides) | 5.3 | Ajuna | ||
| Week 12 | ||||||
| M | 11/23 | The Memory Hierarchy (slides) | 5.5, 5.7, 5.10–5.12 | HW 10 | Brandon | |
| W | 11/25 | Exam 4 | ||||
| Thanksgiving Break | ||||||
| Week 13 | ||||||
| M | 11/30 | Virtual Memory (slides) | 5.4 | Kevin | ||
| W | 12/2 | The I/O Interface (slides) | 6.1, 6.5–6.6 | Larry | ||
| F | 12/4 | Parallel Architectures (slides) | 7.1–7.4 | |||
| Week 14 | ||||||
| M | 12/7 | Synchronization & Cache Coherence (slides) | 2.11, 5.8 | HW 11 | Erin | |
| W | 12/9 | Pause for breath (slides) | Ruth | |||
| F | 12/11 | Course evaluations and wrap-up | Corey | |||
| Finals Week | ||||||
| F | 12/18 | Final Exam | ||||