registers.circ file.
In this assignment, you will build a register file with four 4-bit registers. This register file will reappear along with your ALU from the previous assignment later in the semester when we construct an entire processor datapath in Logisim.
Your grade for this assignment will be determined by how many tests your register file implementation can pass.
Additional consideration will be given to the clarity of organization within your circuits. Wires, gates, and pins should be laid out in a fashion that facilitates comprehension.
Download the starter file registers.circ and complete all of your implementation in this file.
Please do not move or rename any input and output pins in the starter file—this can potentially cause your assignment to fail in the autograder, even if your implementation is otherwise correct.
In the “4-bit register” subcircuit, build a four-bit register from four D flip-flops. Use Logisim’s built-in D flip-flop components, which are available in the explorer pane’s “Memory” category. Your four bit register must have the following inputs and outputs:
output (4 bits)data (4 bits)write_enable (1 bit)data input should be written to the register on a falling clock edge.clock (1 bit)Writing to the register should be controlled by the clock signal with write_enable connected to the flip-flop’s “Enable” pin en (on the bottom of the flip-flop).
The value from data should be stored on the falling clock edge, only when write_enable is high.
Logisim defaults to rising-edge flip-flops, so you will need to change this in the flip-flop’s attribute panel.
In the “4x4 register” subcircuit, build a register file consisting of four copies of your “4-bit register” subcircuit. The register file has the following inputs and outputs:
data (4 bits)write indexoutput (4 bits)read indexread (2 bits)outputwrite (2 bits)write_enable is setwrite_enable (1 bit)data should be written to the register specified by the write index.clock (1 bit)Be sure to thoroughly test your logic circuit before submitting your work. Unfortunately, because this is a sequential logic element, the simple truth-table based test mechanisms used previously no longer work.