Schedule

The schedule below shows the tentative dates for all class topics, readings, and assignments. You should complete all assigned reading before class on the day it is listed. Labs will be available shortly before the assigned lab day. There may be some revisions to the schedule during the semester, but I will make sure to announce these changes in class. If you view this page with JavaScript enabled you can jump to the current week on the schedule, and you should see the next day of class highlighted in the schedule below.

Week 0
Th
Oct 29

Welcome and Introduction

We will begin this course with an overview of what computer organization and architecture is, discuss the basic structure of the course, and get to know each other.

Reading
  • Introduction
    • Patterson & Hennessy – Chapter 1.1
    • (pp. 3–11)
  • Eight Great Ideas in Computer Architecture
    • Patterson & Hennessy – Chapter 1.2
    • (pp. 11–13)
  • Below Your Program
    • Patterson & Hennessy – Chapter 1.3
    • (pp. 13–16)
  • Under the Covers
    • Patterson & Hennessy – Chapter 1.4
    • (pp. 16–24)

F
Oct 30

Logic Gates & Karnaugh Maps

Our first deep dive into architecture will introduce the basic building blocks of a processor—logic gates.

Reading
  • Introduction
    • Patterson & Hennessy – Chapter B.1
    • (pp. B-3–B-4)
  • Gates, Truth Tables, and Logic Equations
    • Patterson & Hennessy – Chapter B.2
    • (pp. B-4–B-9)
  • Focus on Karnaugh Maps
    • Linda Null and Julia Lobur
    • Computer Organization and Architecture – Chapter 3A.1–3A.6
    • (pp. 130–141)
Week 1
M
Nov 2

Combinational Logic

In this course we will often use logic gates to implement specific behaviors. Today we will look at some of the common structures we build from logic gates that we’ll use through the rest of the course.

Reading
  • Combinational Logic
    • Patterson & Hennessy – Chapter B.3
    • (pp. B-9–B-20)
Tu
Nov 3

US Election Day / Lab Working Day

Today is the US general election. If you are eligible to vote in the election and have not already voted by this day, please do so! Normally, this will be a reserved time for you to work with your lab partner(s), but I understand some of you may be unavailable because you are voting. If this is an issue for you, let me know and I can give your group additional time to complete our first full lab. If you are able to work with your group during this time I will be available to answer questions from 8–10am Grinnell time.

 
    W
    Nov 4

    No Class

    Whatever happens in the US general election, it is likely many of us will need some time to process the outcome, if we even know what the outcome is at this point. We will resume regularly-scheduled class meetings on Thursday.

     
      Th
      Nov 5

      Binary Math & ALU Design

      Today, we will discuss the methods we use to perform addition and subtraction with binary numbers. We’ll spend some time thinking about how we can build circuits to perform these operations for us.

      Reading
      • Signed and Unsigned Numbers
        • Patterson & Hennessy – Chapter 2.4
        • (pp. 73–80)
      • Addition and Subtraction
        • Patterson & Hennessy – Chapter 3.2
        • (pp. 178–183)
      • Constructing a Basic Arithmetic Logic Unit
        • Patterson & Hennessy – Chapter B.5
        • (pp. B-26–B-35)
      F
      Nov 6

      Lab Working Day

      Use this time to work with your partner(s) on the current lab. There is no synchronous class meeting, but I will be available during class time to answer your questions about the lab.

       
        Due
        Week 2
        M
        Nov 9

        Sequential Logic

        While we’ve seen a number of ways to use logic gates to compute output values from input values, we have not yet discussed circuits with memory. Sequential logic allows us to build circuits that store information. We’ll discuss a few of these circuits and think about where they may be useful.

        Reading
        • Clocks
          • Patterson & Hennessy – Chapter B.7
          • (pp. B-48–B-50)
        • Memory Elements: Flip-Flops, Latches, and Registers
          • Patterson & Hennessy – Chapter B.8
          • (pp. B-50–B-58)
        Tu
        Nov 10

        Lab Working Day

        Use this time to work with your partner(s) on the current lab. There is no synchronous class meeting, but I will be available during class time to answer your questions about the lab.

         
          W
          Nov 11

          Memory

          The sequential logic we’ve seen so far allow us to store small amounts of information, but computers have enormous amounts of information to store. Today, we will look at the structures that are used to store large amounts of information.

          Reading
          • Memory Elements: SRAMs and DRAMs
            • Patterson & Hennessy – Chapter B.9
            • (pp. B-58–B-67)

          Th
          Nov 12

          Assembly & Machine Language

          So far, this course has focused on designing and understanding circuits that perform a specific action for us, but the computers we use regularly are capable of performing arbitrary work. Today, we will look at how we can communciate arbitrary tasks to a general purpose computer.

          Reading
          • Introduction
            • Patterson & Hennessy – Chapter 2.1
            • (pp. 62–63)
          • Operations of the Computer Hardware
            • Patterson & Hennessy – Chapter 2.2
            • (pp. 63–66)
          • Operands of the Computer Hardware
            • Patterson & Hennessy – Chapter 2.3
            • (pp. 66–73)
          • Representing Instructions in the Computer
            • Patterson & Hennessy – Chapter 2.5
            • (pp. 80–87)
          • Logical Operations
            • Patterson & Hennessy – Chapter 2.6
            • (pp. 87–90)
          Due Assigned
          F
          Nov 13

          Lab Working Day

          Use this time to work with your partner(s) on the current lab. There is no synchronous class meeting, but I will be available during class time to answer your questions about the lab.

           
            Week 3
            M
            Nov 16

            Making Decisions

            Reading
            • Instructions for Making Decisions
              • Patterson & Hennessy – Chapter 2.7
              • (pp. 90–96)
            Due Assigned
            Tu
            Nov 17

            Lab Working Day

            Use this time to work with your partner(s) on the current lab. There is no synchronous class meeting, but I will be available during class time to answer your questions about the lab.

             
              W
              Nov 18

              Supporting Procedures

              Reading
              • Supporting Procedures in Computer Hardware
                • Patterson & Hennessy – Chapter 2.8
                • (pp. 96–106)

              Th
              Nov 19

              Strings, Addressing, & Arrays

              Reading
              • Communicating with People
                • Patterson & Hennessy – Chapter 2.9
                • (pp. 106–111)
              • MIPS Addressing for 32-Bit Immediates and Addresses
                • Patterson & Hennessy – Chapter 2.10
                • (pp. 111–121)
              • Arrays versus Pointers
                • Patterson & Hennessy – Chapter 2.14
                • (pp. 141–145)
              F
              Nov 20

              Lab Working Day

              Use this time to work with your partner(s) on the current lab. There is no synchronous class meeting, but I will be available during class time to answer your questions about the lab.

               
                Due
                Week 4
                M
                Nov 23

                Datapath

                Reading
                • Introduction
                  • Patterson & Hennessy – Chapter 4.1
                  • (pp. 244–248)
                • Logic Design Conventions
                  • Patterson & Hennessy – Chapter 4.2
                  • (pp. 248–251)
                • Building a Datapath
                  • Patterson & Hennessy – Chapter 4.3
                  • (pp. 251–259)
                Tu
                Nov 24

                Lab Working Day

                Use this time to work with your partner(s) on the current lab. There is no synchronous class meeting, but I will be available during class time to answer your questions about the lab.

                W
                Nov 25

                Control

                Reading
                • A Simple Implementation Scheme
                  • Patterson & Hennessy – Chapter 4.4
                  • (pp. 259–272)
                Th
                Nov 26

                No Class – Thanksgiving Day

                 
                  F
                  Nov 27

                  Lab Working Day

                  Use this time to work with your partner(s) on the current lab. There is no synchronous class meeting, but I will be available during class time to answer your questions about the lab.

                   
                    Week 5
                    M
                    Nov 30

                    Lab Working Day

                    Use this time to work with your partner(s) on the current lab. There is no synchronous class meeting, but I will be available during class time to answer your questions about the lab.

                    Tu
                    Dec 1

                    Pipelining

                    Reading
                    • An Overview of Pipelining
                      • Patterson & Hennessy – Chapter 4.5
                      • (pp. 272–286)
                    • Pipelined Datapath and Control
                      • Patterson & Hennessy – Chapter 4.6
                      • (pp. 286–303)
                    Due

                    W
                    Dec 2

                    Data Hazards

                    Reading
                    • Data Hazards: Forwarding versus Stalling
                      • Patterson & Hennessy – Chapter 4.7
                      • (pp. 303–316)

                    Th
                    Dec 3

                    Control Hazards

                    Reading
                    • Control Hazards
                      • Patterson & Hennessy – Chapter 4.8
                      • (pp. 316–325)
                    F
                    Dec 4

                    Lab Working Day

                    Use this time to work with your partner(s) on the current lab. There is no synchronous class meeting, but I will be available during class time to answer your questions about the lab.

                     
                      Due
                      Week 6
                      M
                      Dec 7
                      Reading
                      • Introduction
                        • Patterson & Hennessy – Chapter 5.1
                        • (pp. 374–378)
                      • Memory Technologies
                        • Patterson & Hennessy – Chapter 5.2
                        • (pp. 378–383)
                      • The Basics of Caches
                        • Patterson & Hennessy – Chapter 5.3
                        • (pp. 383–398)
                      • Measuring and Improving Cache Performance
                        • Patterson & Hennessy – Chapter 5.4
                        • (pp. 398–418)
                      • Using a Finite-State Machine to Control a Simple Cache
                        • Patterson & Hennessy – Chapter 5.9
                        • (pp. 461–466)
                      Tu
                      Dec 8

                      Lab Working Day

                      Use this time to work with your partner(s) on the current lab. There is no synchronous class meeting, but I will be available during class time to answer your questions about the lab.

                       
                        Due
                        W
                        Dec 9

                        Memory Hierarchy

                        Reading
                        • Virtual Memory
                          • Patterson & Hennessy – Chapter 5.7
                          • (pp. 427–454)
                        • A Common Framework for Memory Hierarchy
                          • Patterson & Hennessy – Chapter 5.8
                          • (pp. 454–461)

                        Th
                        Dec 10

                        Instruction-Level Parallelism

                        Reading
                        • Parallelism via Instructions
                          • Patterson & Hennessy – Chapter 4.10
                          • (pp. 332–344)
                        • Fallacies and Pitfalls
                          • Patterson & Hennessy – Chapter 4.14
                          • (pp. 355–356)
                        • Concluding Remarks
                          • Patterson & Hennessy – Chapter 4.15
                          • (pp. 356–357)
                        F
                        Dec 11

                        Lab Working Day

                        Use this time to work with your partner(s) on the current lab. There is no synchronous class meeting, but I will be available during class time to answer your questions about the lab.

                         
                          Due
                          Week 7
                          M
                          Dec 14

                          Parallelism & Synchronization

                          Reading
                          • Introduction
                            • Patterson & Hennessy – Chapter 6.1
                            • (pp. 502–504)
                          • The Difficulty of Creating Parallel Processing Programs
                            • Patterson & Hennessy – Chapter 6.2
                            • (pp. 504–509)
                          • SISD, MIMD, SIMD, SPMD, and Vector
                            • Patterson & Hennessy – Chapter 6.3
                            • (pp. 509–516)
                          Tu
                          Dec 15

                          Lab Working Day

                          Use this time to work with your partner(s) on the current lab. There is no synchronous class meeting, but I will be available during class time to answer your questions about the lab.

                           
                            W
                            Dec 16

                            Parallel Architectures

                            Reading
                            • Hardware Multithreading
                              • Patterson & Hennessy – Chapter 6.4
                              • (pp. 516–519)
                            • Multicore and Other Shared Memory Multiprocessors
                              • Patterson & Hennessy – Chapter 6.5
                              • (pp. 519–524)
                            • Introduction to Graphics Processing Units
                              • Patterson & Hennessy – Chapter 6.6
                              • (pp. 524–531)
                            Due

                            Th
                            Dec 17
                            Reading
                            Finals Week
                            Tu
                            Dec 22

                            Work Due

                             
                              Due