Schedule
The schedule below shows the tentative dates for all class topics, readings, and assignments. You should complete all assigned reading before class on the day it is listed. Labs will be available shortly before the assigned lab day. There may be some revisions to the schedule during the semester, but I will make sure to announce these changes in class. If you view this page with JavaScript enabled you can jump to the current week on the schedule, and you should see the next day of class highlighted in the schedule below.
Week 1
M
Jan 22
Jan 22
Introduction
Reading
-
Sections 1.1-1.8: Introduction through The Sea Change: The Switch from Uniprocessors to Multiprocessors
- Patterson & Hennessy
- (pp. 2–46)
W
Jan 24
Jan 24
Electricity: Circuits and Transistors
Assigned
F
Jan 26
Jan 26
Lab Day
Reading
-
B.1 – Introduction
- Patterson & Hennessy
- (pp. B-693–B-694)
-
B.2 – Gates, Truth Tables, and Logic Equations
- Patterson & Hennessy
- (pp. B-694–B-699)
Activities
- Week 1 Quiz
Assigned
Week 2
M
Jan 29
Jan 29
No Class Today
Due
- Assignment: Welcome (11:59pm)
W
Jan 31
Jan 31
Karnaugh Maps
Reading
-
Section 3A.1–3A.6
- Null and Lobur (available on eReserves)
- (pp. 130–141)
F
Feb 2
Feb 2
Combinational Logic
Reading
-
B.3 – Combinational Logic
- Patterson & Hennessy
- (pp. B-699–B-710)
Activities
- Week 2 Quiz
- Mini-Lab: Combinational Logic
Due
- Lab: Logic Gates (before class)
Week 3
M
Feb 5
Feb 5
Binary Math
Reading
-
Section 2.4 – Signed and Unsigned Numbers
- Patterson & Hennessy
- (pp. 79–86)
-
Section 3.2 – Addition and Subtraction
- Patterson & Hennessy
- (pp. 188–193)
Assigned
W
Feb 7
Feb 7
No Class Today
F
Feb 9
Feb 9
Lab Day
Week 4
M
Feb 12
Feb 12
No Class Today
Due
-
Assignment: Combinational Logic
- (deadline extended)
W
Feb 14
Feb 14
ALU Design
Reading
-
B.5 – Constructing a Basic Arithmetic Logic Unit
- Patterson & Hennessy
- (pp. B-716–B-728)
Assigned
Due
- Assignment: Combinational Logic (11:59pm)
F
Feb 16
Feb 16
Lab Day
Week 5
M
Feb 19
Feb 19
Sequential Logic
Reading
-
B.7 – Clocks
- Patterson & Hennessy
- (pp. B-738–B-740)
-
B.8 – Memory Elements: Flip-Flops, Latches, and Registers
- Patterson & Hennessy
- (pp. B-740–B-748)
Activities
W
Feb 21
Feb 21
Memory: SRAM and DRAM
Reading
-
B.9 – Memory Elements: SRAMs and DRAMs
- Patterson & Hennessy
- (pp. B-748–B-757)
Assigned
Due
- Assignment: Logisim ALU (11:59pm)
F
Feb 23
Feb 23
Lab Day
Week 6
M
Feb 26
Feb 26
Exam 1
W
Feb 28
Feb 28
Assembly and Machine Language
Reading
-
Section 2.1 – Introduction
- Patterson & Hennessy
- (pp. 66–69)
-
Section 2.2 – Operations of the Computer Hardware
- Patterson & Hennessy
- (pp. 69–72)
-
Section 2.3 – Operands of the Computer Hardware
- Patterson & Hennessy
- (pp. 72–79)
-
Section 2.5 – Representing Instructions in the Computer
- Patterson & Hennessy
- (pp. 86–93)
F
Mar 1
Mar 1
Lab Day
Week 7
M
Mar 4
Mar 4
Logic and Making Decisions
Reading
-
Section 2.6 – Logical Operations
- Patterson & Hennessy
- (pp. 93–96)
-
Section 2.7 – Instructions for Making Decisions
- Patterson & Hennessy
- (pp. 96–102)
Assigned
Due
- Assignment: Logisim Register File (11:59pm)
W
Mar 6
Mar 6
Supporting Procedures
Reading
-
Section 2.8 – Supporting Procedures in Computer Hardware
- Patterson & Hennessy
- (pp. 102–112)
F
Mar 8
Mar 8
Lab Day
Week 8
M
Mar 11
Mar 11
Pause for Breath
W
Mar 13
Mar 13
Strings, Addressing, and Arrays
Reading
-
Section 2.9 – Communicating with People
- Patterson & Hennessy
- (pp. 112–118)
-
Section 2.10 – MIPS Addressing for 32-Bit Immediates and Addresses
- Patterson & Hennessy
- (pp. 118–127)
-
Section 2.14 – Arrays versus Pointers
- Patterson & Hennessy
- (pp. 147–151)
Assigned
F
Mar 15
Mar 15
Program Translation
Reading
-
Section 2.12 – Translating and Starting a Program
- Patterson & Hennessy
- (pp. 129–138)
-
Section 2.13 – A C Sort Example to Put It All Together
- Patterson & Hennessy
- (pp. 138–147)
Activities
- Week 8 Quiz
Due
- Assignment: MIPS Basics (11:59pm)
- Lab: Blinking Lights (before class)
Spring Break
Week 9
M
Apr 1
Apr 1
Out sick
W
Apr 3
Apr 3
Arrays, Datapath
Reading
-
Section 2.14 – Arrays versus Pointers
- Patterson & Hennessy
- (pp. 147–151)
-
Section 4.1 – Introduction
- Patterson & Hennessy
- (pp. 254–260)
-
Section 4.2 – Logic Design Conventions
- Patterson & Hennessy
- (pp. 260–263)
-
Section 4.3 – Building a Datapath
- Patterson & Hennessy
- (pp. 263–271)
Activities
F
Apr 5
Apr 5
Lab Day
Week 10
M
Apr 8
Apr 8
Exam 2
W
Apr 10
Apr 10
Control
Reading
-
Section 4.4 – A Simple Implementation Scheme
- Patterson & Hennessy
- (pp. 271–284)
F
Apr 12
Apr 12
Lab Day
Reading
-
D.1 – Introduction
- Patterson & Hennessy
- (pp. D-2–D-4)
-
D.3 – Implementing Finite-State Machine Control
- Patterson & Hennessy
- (pp. D-8–D-22)
Activities
- Week 10 Quiz
Assigned
Due
- Lab: Play a Song (before class)
Week 11
M
Apr 15
Apr 15
Pipelining
Reading
-
Section 4.6 – An Overview of Pipelining
- Patterson & Hennessy
- (pp. 285–298)
-
Section 4.7 – Pipelined Datapath and Control
- Patterson & Hennessy
- (pp. 298–315)
W
Apr 17
Apr 17
Data Hazards
Reading
-
Section 4.8 – Data Hazards: Forwarding versus Stalling
- Patterson & Hennessy
- (pp. 315–328)
F
Apr 19
Apr 19
Lab Day
Week 12
M
Apr 22
Apr 22
No Class Today
W
Apr 24
Apr 24
Control Hazards and Exceptions
Reading
-
Section 4.9 – Control Hazards
- Patterson & Hennessy
- (pp. 328–337)
-
Section 4.10 – Exceptions
- Patterson & Hennessy
- (pp. 337–344)
F
Apr 26
Apr 26
Lab Day
Week 13
Su
Apr 28
Apr 28
Work Due
Due
- Lab: Build a Datapath, part II (11:59pm)
M
Apr 29
Apr 29
Instruction-Level Parallelism
Reading
-
Section 4.11 – Parallelism via Instructions
- Patterson & Hennessy
- (pp. 344–358)
-
Section 4.15 – Fallacies and Pitfalls
- Patterson & Hennessy
- (pp. 369–370)
-
Section 4.16 – Concluding Remarks
- Patterson & Hennessy
- (pp. 370–371)
W
May 1
May 1
Caches
Reading
-
Section 5.1 – Introduction
- Patterson & Hennessy
- (pp. 392–396)
-
Section 5.2 – Memory Technologies
- Patterson & Hennessy
- (pp. 396–401)
-
Section 5.3 – The Basics of Caches
- Patterson & Hennessy
- (pp. 401–416)
-
Section 5.4 – Measuring and Improving Cache Performance
- Patterson & Hennessy
- (pp. 416–436)
F
May 3
May 3
Lab Day
Reading
-
Section 5.9 – Using a Finite-State Machine to Control a Simple Cache
- Patterson & Hennessy
- (pp. 479–484)
Activities
- Week 13 Quiz
Assigned
Week 14
Su
May 5
May 5
Work Due
Due
- Lab: Build a Datapath, part III (11:59pm)
M
May 6
May 6
Memory Hierarchy
Reading
-
Section 5.7 – Virtual Memory
- Patterson & Hennessy
- (pp. 446–472)
-
Section 5.8 – A Common Framework for Memory Hierarchy
- Patterson & Hennessy
- (pp. 472–479)
W
May 8
May 8
Parallelism
Reading
-
Section 6.1 – Introduction
- Patterson & Hennessy
- (pp. 524–528)
-
Section 6.2 – The Difficulty of Creating Parallel Processing Programs
- Patterson & Hennessy
- (pp. 528–533)
-
Section 6.3 – SISD, MIMD, SIMD, SPMD, and Vector
- Patterson & Hennessy
- (pp. 533–540)
F
May 10
May 10
Wrap Up
Finals Week
Tu
May 14
May 14
Final Exam (2–5pm)
Activities
- Final Exam
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